Tutorial: Zhinst hardware verification#

See also

The complete source code of this tutorial can be found in

T_verification_programs.ipynb

Introduction#

This tutorial gives an overview of how to use the zhinst_backend for quantify-scheduler. The example we follow in this notebook corresponds to a standard circuit QED measurement setup in which readout is performed by generating a pulse on a UFHQA, send to the device and the returning signal is measured in transmission using the same UFHQA, and an HDAWG is then used to generate the control pulses. We set up this test setup so that it is easy to verify the hardware is behaving correctly and that it can be used for real experiments with minimal modifications.

In how to connect we discuss how to set up the test setup, connect all the cables, and use quantify to connect to the hardware. In how to configure we discuss how to write a hardware configuration file that can be used to compile instructions for the Zurich Instruments hardware. In verification programs we go over how to write and compile several verification programs, how to verify that these are correct, and how to execute these on the physical hardware.

How to connect#

Note

This documentation is a work in progress. See issue #237. Improvements to this tutorial will include adding instructions on how to connect the hardware and how to set up the initialization script as well as more example programs.

How to create an hardware compilation configuration#

Verifying the hardware compilation#

quantify-scheduler comes with several built-in verification programs in the verification module. Here we will start by building and compiling the first schedule by hand to show how one can construct such a schedule and debug it, before giving an overview of test programs.

Bining and averaging - AWG staircase#

Description#

In this schedule, we will play pulses of increasing amplitude on the HDAWG. These pulses are modulated with a local oscillator so that they appear at the same frequency as the readout pulse. This ensures that they are visible in the acquired signal.

Expected outcome#

One would expect to see a monotonic increase in the measured amplitude. The actual amplitudes would probably not match the input amplitudes 1-to-1 because there is likely some loss on the signal path from the up- and down-conversion. Additionally, depending on the overlap between the pulse and the integration window, the average measured voltage will be slightly lower, and the phase can be slightly different resulting in not all signals being in the I-quadrature.

Creating the staircase program#

We start by manually recreating the awg_staircase_sched(), a schedule in which (modulated) square pulses are played on an HDAWG and the UHFQA is triggered subsequently to observe the result of that schedule.

# import statements required to make a schedule

import numpy as np

from quantify_scheduler import Schedule
from quantify_scheduler.operations.acquisition_library import SSBIntegrationComplex
from quantify_scheduler.operations.pulse_library import IdlePulse, SquarePulse
from quantify_scheduler.resources import ClockResource
pulse_amps = np.linspace(0.05, 0.9, 3)
repetitions = 1024
init_duration = 4000e-6  # 4us should allow for plenty of wait time
mw_port = "q0:mw"
ro_port = "q0:res"
mw_clock = "q0.01"  # chosen to correspond to values in the hardware compilation cfg
ro_clock = "q0.ro"
readout_frequency = (
    6.5e9  # this frequency will be used for both the AWG pulse as well as
)
# for the readout.

pulse_duration = 1e-6
acq_channel = 0
integration_time = 2e-6
acquisition_delay = 0


sched = Schedule(name="AWG staircase", repetitions=repetitions)

sched.add_resource(ClockResource(name=mw_clock, freq=readout_frequency))
sched.add_resource(ClockResource(name=ro_clock, freq=readout_frequency))
pulse_amps = np.asarray(pulse_amps)


for acq_index, pulse_amp in enumerate(pulse_amps):

    sched.add(IdlePulse(duration=init_duration))

    pulse = sched.add(
        SquarePulse(
            duration=pulse_duration,
            amp=pulse_amp,
            port=mw_port,
            clock=mw_clock,
        ),
        label=f"SquarePulse_{acq_index}",
    )

    sched.add(
        SSBIntegrationComplex(
            duration=integration_time,
            port=ro_port,
            clock=ro_clock,
            acq_index=acq_index,
            acq_channel=acq_channel,
        ),
        ref_op=pulse,
        ref_pt="start",
        rel_time=acquisition_delay,
        label=f"Acquisition_{acq_index}",
    )

sched

Schedule "AWG staircase" containing (7) 9  (unique) operations.

Now that we have generated the schedule we can compile it and verify if the hardware output is correct.

from quantify_scheduler.backends.circuit_to_device import DeviceCompilationConfig
from quantify_scheduler.backends.graph_compilation import SerialCompiler
from quantify_scheduler.device_under_test.quantum_device import QuantumDevice
from quantify_scheduler.schemas.examples import utils
from quantify_scheduler.schemas.examples.device_example_cfgs import (
    example_transmon_cfg,
)

quantum_device = QuantumDevice("DUT")

transmon_device_cfg = DeviceCompilationConfig.model_validate(example_transmon_cfg)
quantum_device.hardware_config(utils.load_json_example_scheme("zhinst_hardware_compilation_config.json"))

compiler = SerialCompiler(name="compiler")
comp_sched = compiler.compile(
    schedule=sched, config=quantum_device.generate_compilation_config()
)
The timing table#

The ScheduleBase.timing_table can be used after the absolute timing has been determined. It gives an overview of all operations in the schedule at the quantum-device level.

# Pandas dataframes do not render correctly in the sphinx documentation environment. See issue #238.
comp_sched.timing_table

  waveform_op_id port clock abs_time duration is_acquisition operation wf_idx operation_hash
0 IdlePulse(duration=0.004)_acq_0 None cl0.baseband 0.0 ns 4,000,000.0 ns False IdlePulse(duration=0.004) 0 -8313245398570424028
1 SquarePulse(amp=0.05,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0 q0:mw q0.01 4,000,000.0 ns 1,000.0 ns False SquarePulse(amp=0.05,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0) 0 -1516282948846237773
2 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=0,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 4,000,000.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=0,bin_mode='average',phase=0,t0=0) 0 -1414757231151268374
3 IdlePulse(duration=0.004)_acq_0 None cl0.baseband 4,002,000.0 ns 4,000,000.0 ns False IdlePulse(duration=0.004) 0 -8313245398570424028
4 SquarePulse(amp=0.475,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0 q0:mw q0.01 8,002,000.0 ns 1,000.0 ns False SquarePulse(amp=0.475,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0) 0 -8776100988860567888
5 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=1,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 8,002,000.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=1,bin_mode='average',phase=0,t0=0) 0 -7457024832271362313
6 IdlePulse(duration=0.004)_acq_0 None cl0.baseband 8,004,000.0 ns 4,000,000.0 ns False IdlePulse(duration=0.004) 0 -8313245398570424028
7 SquarePulse(amp=0.9,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0 q0:mw q0.01 12,004,000.0 ns 1,000.0 ns False SquarePulse(amp=0.9,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0) 0 14206750273485196
8 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=2,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 12,004,000.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=2,bin_mode='average',phase=0,t0=0) 0 4084677390208054071
The hardware timing table#

The CompiledSchedule.hardware_timing_table is populated during the hardware compilation. It gives an overview of all operations in the schedule at the control-electronics layer. This means that the signals are corrected for effects such as gain and latency, and that modulations have been applied.

The “waveform_id” key can be used to find the numerical waveforms in CompiledSchedule.hardware_waveform_dict.

comp_sched.hardware_timing_table

  waveform_op_id port clock abs_time duration is_acquisition operation wf_idx operation_hash hardware_channel clock_cycle_start sample_start waveform_id
0 IdlePulse(duration=0.004)_acq_0 None cl0.baseband 0.0 ns 4,000,000.0 ns False IdlePulse(duration=0.004) 0 -8313245398570424028 None nan nan IdlePulse(duration=0.004)_acq_0_sample:nan_phase:0.0
2 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=0,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 4,000,000.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=0,bin_mode='average',phase=0,t0=0) 0 -1414757231151268374 ic_uhfqa0.awg0 900,000.0 0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0
1 SquarePulse(amp=0.05,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0 q0:mw q0.01 4,000,190.0 ns 1,000.0 ns False SquarePulse(amp=0.05,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0) 0 -1516282948846237773 ic_hdawg0.awg0 1,200,057.0 0.0 SquarePulse(amp=0.05,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0_sample:0.0_phase:0.0
3 IdlePulse(duration=0.004)_acq_0 None cl0.baseband 4,002,000.0 ns 4,000,000.0 ns False IdlePulse(duration=0.004) 0 -8313245398570424028 None nan nan IdlePulse(duration=0.004)_acq_0_sample:nan_phase:0.0
5 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=1,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 8,002,000.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=1,bin_mode='average',phase=0,t0=0) 0 -7457024832271362313 ic_uhfqa0.awg0 1,800,450.0 0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0
4 SquarePulse(amp=0.475,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0 q0:mw q0.01 8,002,190.0 ns 1,000.0 ns False SquarePulse(amp=0.475,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0) 0 -8776100988860567888 ic_hdawg0.awg0 2,400,657.0 0.0 SquarePulse(amp=0.475,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0_sample:0.0_phase:0.0
6 IdlePulse(duration=0.004)_acq_0 None cl0.baseband 8,004,000.0 ns 4,000,000.0 ns False IdlePulse(duration=0.004) 0 -8313245398570424028 None nan nan IdlePulse(duration=0.004)_acq_0_sample:nan_phase:0.0
8 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=2,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 12,004,000.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=2,bin_mode='average',phase=0,t0=0) 0 4084677390208054071 ic_uhfqa0.awg0 2,700,900.0 0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0
7 SquarePulse(amp=0.9,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0 q0:mw q0.01 12,004,190.0 ns 1,000.0 ns False SquarePulse(amp=0.9,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0) 0 14206750273485196 ic_hdawg0.awg0 3,601,257.0 0.0 SquarePulse(amp=0.9,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0_sample:0.0_phase:0.0
The hardware waveform dict#
comp_sched.hardware_waveform_dict

{
    "SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0": array([ 1.        +1.j        ,  1.40883205+0.12325683j,
        1.15845593-0.81115958j, ..., -1.3660254 +0.3660254j ,
       -0.81115958+1.15845593j,  0.12325683+1.40883205j]),
    "SquarePulse(amp=0.05,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0_sample:0.0_phase:0.0": array([0.04873397+0.j        , 0.04705799-0.01327714j,
       0.04217509-0.02564946j, ..., 0.03450222+0.03627381j,
       0.04223463+0.02564946j, 0.04708881+0.01327714j]),
    "SquarePulse(amp=0.475,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0_sample:0.0_phase:0.0": array([0.46297273+0.j        , 0.44705092-0.1261328j ,
       0.40066333-0.24366986j, ..., 0.32777112+0.34460122j,
       0.40122896+0.24366986j, 0.44734371+0.1261328j ]),
    "SquarePulse(amp=0.9,duration=1e-06,port='q0:mw',clock='q0.01',reference_magnitude=None,t0=0)_acq_0_sample:0.0_phase:0.0": array([0.87721149+0.j        , 0.84704385-0.23898846j,
       0.75915158-0.46169026j, ..., 0.62104001+0.65292863j,
       0.76022329+0.46169026j, 0.84759861+0.23898846j])
}
The compiled instructions#

The compiled instructions can be found in the compiled_instructions of the compiled schedule.

comp_sched.compiled_instructions

{
    'ic_hdawg0': ZIDeviceConfig(
        name='ic_hdawg0',
        settings_builder=<quantify_scheduler.backends.zhinst.settings.ZISettingsBuilder object at 0x7f8dcb312370>,
        acq_config=None
    ),
    'generic': {
        'lo0.ch1.frequency': 6600000000.0,
        'lo0.power': 13,
        'lo1.frequency': 6300000000.0,
        'lo1.power': 16
    },
    'ic_uhfqa0': ZIDeviceConfig(
        name='ic_uhfqa0',
        settings_builder=<quantify_scheduler.backends.zhinst.settings.ZISettingsBuilder object at 0x7f8dcb312c10>,
        acq_config=ZIAcquisitionConfig(
            n_acquisitions=3,
            resolvers={
                0: functools.partial(<function result_acquisition_resolver at 0x7f8dcb3de820>, result_nodes=['qas/0/result/data/0/wave', 'qas/0/result/data/1/wave'])
            },
            bin_mode=<BinMode.AVERAGE: 'average'>,
            acq_protocols={0: 'SSBIntegrationComplex'}
        )
    )
}

The settings for the Zurich Instruments instruments are stored as a ZIDeviceConfig, of which the settings_builder contains the ZISettingsBuilder containing both the settings to set on all the nodes in the Zurich Instruments drivers as well as the compiled seqc instructions.

# the .as_dict method can be used to generate a "readable" overview of the settings.
hdawg_settings_dict = (
    comp_sched.compiled_instructions["ic_hdawg0"].settings_builder.build().as_dict()
)
# hdawg_settings_dict
hdawg_settings_dict

{
    'sigouts/*/on': 0,
    'awgs/*/single': 1,
    'system/awg/channelgrouping': 0,
    'awgs/0/time': 0,
    'awgs/1/time': 0,
    'awgs/2/time': 0,
    'awgs/3/time': 0,
    'sigouts/0/on': 1,
    'sigouts/1/on': 1,
    'awgs/0/outputs/0/gains/0': 1,
    'awgs/0/outputs/1/gains/1': 1,
    'sigouts/0/offset': -0.0542,
    'sigouts/1/offset': -0.0328,
    'awgs/0/commandtable/data': '{"header":{"version":"0.2","partial":false},"table":[{"index":0,"waveform":{"index":0,"length":2400}},{"index":1,"waveform":{"index":1,"length":2400}},{"index":2,"waveform":{"index":2,"length":2400}}]}',
    'awgs/0/waveform/waves/0': array([1596,    0, 1541, ...,  840, 1542,  435], dtype=int16),
    'awgs/0/waveform/waves/1': array([15170,     0, 14648, ...,  7984, 14658,  4132], dtype=int16),
    'awgs/0/waveform/waves/2': array([28743,     0, 27755, ..., 15128, 27773,  7830], dtype=int16),
    'compiler/sourcestring': {
        0: '// Generated by quantify-scheduler.\n// Variables\nvar __repetitions__ = 1024;\nwave w0 = placeholder(2400);\nwave w1 = placeholder(2400);\nwave w2 = placeholder(2400);\n\n// Operations\nassignWaveIndex(w0, w0, 0);\nassignWaveIndex(w1, w1, 1);\nassignWaveIndex(w2, w2, 2);\nsetTrigger(0);\t//  n_instr=1\nrepeat(__repetitions__)\n{\n  setTrigger(AWG_MARKER1 + AWG_MARKER2);\t//  n_instr=2\n  wait(1200052);\t\t// clock=2\t n_instr=3\n  executeTableEntry(0);\t// clock=1200057 pulse=0 n_instr=0\n  wait(1200597);\t\t// clock=1200057\t n_instr=3\n  executeTableEntry(1);\t// clock=2400657 pulse=1 n_instr=0\n  wait(1200597);\t\t// clock=2400657\t n_instr=3\n  executeTableEntry(2);\t// clock=3601257 pulse=2 n_instr=0\n  setTrigger(0);\t// clock=3601257 n_instr=1\n  wait(539);\t\t// clock=3601258, dead time to ensure total schedule duration\t n_instr=3\n}\n'
    }
}

The compiler source string for each awg channel can be printed to see the instructions the ZI hardware will execute. The clock-cycles are tracked by the assembler backend and can be compared to the hardware_timing_table.

awg_index = 0
print(hdawg_settings_dict["compiler/sourcestring"][awg_index])
// Generated by quantify-scheduler.
// Variables
var __repetitions__ = 1024;
wave w0 = placeholder(2400);
wave w1 = placeholder(2400);
wave w2 = placeholder(2400);

// Operations
assignWaveIndex(w0, w0, 0);
assignWaveIndex(w1, w1, 1);
assignWaveIndex(w2, w2, 2);
setTrigger(0);	//  n_instr=1
repeat(__repetitions__)
{
  setTrigger(AWG_MARKER1 + AWG_MARKER2);	//  n_instr=2
  wait(1200052);		// clock=2	 n_instr=3
  executeTableEntry(0);	// clock=1200057 pulse=0 n_instr=0
  wait(1200597);		// clock=1200057	 n_instr=3
  executeTableEntry(1);	// clock=2400657 pulse=1 n_instr=0
  wait(1200597);		// clock=2400657	 n_instr=3
  executeTableEntry(2);	// clock=3601257 pulse=2 n_instr=0
  setTrigger(0);	// clock=3601257 n_instr=1
  wait(539);		// clock=3601258, dead time to ensure total schedule duration	 n_instr=3
}
# the .as_dict method can be used to generate a "readable" overview of the settings.
uhfqa_settings_dict = (
    comp_sched.compiled_instructions["ic_uhfqa0"].settings_builder.build().as_dict()
)
# uhfqa_settings_dict
uhfqa_settings_dict

{
    'awgs/0/single': 1,
    'qas/0/rotations/*': (1+1j),
    'qas/0/integration/sources/*': 0,
    'sigouts/0/on': 1,
    'sigouts/1/on': 1,
    'awgs/0/time': 0,
    'qas/0/integration/weights/0/real': array([1.        , 1.40883205, 1.15845593, ..., 0.        , 0.        ,
       0.        ]),
    'qas/0/integration/weights/1/real': array([ 1.        ,  0.12325683, -0.81115958, ...,  0.        ,
        0.        ,  0.        ]),
    'qas/0/integration/weights/2/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/3/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/4/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/5/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/6/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/7/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/8/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/9/real': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/0/imag': array([ 1.        ,  0.12325683, -0.81115958, ...,  0.        ,
        0.        ,  0.        ]),
    'qas/0/integration/weights/1/imag': array([-1.        , -1.40883205, -1.15845593, ..., -0.        ,
       -0.        , -0.        ]),
    'qas/0/integration/weights/2/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/3/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/4/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/5/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/6/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/7/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/8/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'qas/0/integration/weights/9/imag': array([0., 0., 0., ..., 0., 0., 0.]),
    'sigouts/0/offset': 0.0,
    'sigouts/1/offset': 0.0,
    'awgs/0/waveform/waves/0': array([23258, 23258, 32766, ..., 26943,  2866, 32766], dtype=int16),
    'qas/0/integration/mode': 0,
    'qas/0/integration/length': 3600,
    'qas/0/result/enable': 1,
    'qas/0/monitor/enable': 0,
    'qas/0/delay': 0,
    'qas/0/result/mode': 0,
    'qas/0/result/source': 7,
    'qas/0/result/length': 3,
    'qas/0/result/averages': 1024,
    'qas/0/result/reset': 1,
    'qas/0/monitor/reset': 1,
    'compiler/sourcestring': {
        0: '// Generated by quantify-scheduler.\n// Variables\nvar __repetitions__ = 1024;\nwave w0 = "ic_uhfqa0_awg0_wave0";\n\n// Operations\nrepeat(__repetitions__)\n{\n  waitDigTrigger(2, 1);\t// \t// clock=0\n  wait(900000);\t\t// clock=0\t n_instr=900000\n  startQA(QA_INT_ALL, true);\t// clock=900000 n_instr=7\n  wait(900443);\t\t// clock=900007\t n_instr=900443\n  startQA(QA_INT_ALL, true);\t// clock=1800450 n_instr=7\n  wait(900443);\t\t// clock=1800457\t n_instr=900443\n  startQA(QA_INT_ALL, true);\t// clock=2700900 n_instr=7\n}\n'
    }
}
awg_index = 0
print(uhfqa_settings_dict["compiler/sourcestring"][awg_index])
// Generated by quantify-scheduler.
// Variables
var __repetitions__ = 1024;
wave w0 = "ic_uhfqa0_awg0_wave0";

// Operations
repeat(__repetitions__)
{
  waitDigTrigger(2, 1);	// 	// clock=0
  wait(900000);		// clock=0	 n_instr=900000
  startQA(QA_INT_ALL, true);	// clock=900000 n_instr=7
  wait(900443);		// clock=900007	 n_instr=900443
  startQA(QA_INT_ALL, true);	// clock=1800450 n_instr=7
  wait(900443);		// clock=1800457	 n_instr=900443
  startQA(QA_INT_ALL, true);	// clock=2700900 n_instr=7
}

Verification programs#

quantify-scheduler comes with several test programs that can be used to verify that the software and the hardware are configured and functioning correctly. You should be able to run this notebook on your setup directly if you replace the mock_setup initialization with your initialization script.

Note

This documentation is a work in progress. See issue #237. Here we provide an overview of schedules that are used to verify different kinds of functionality. This section will be expanded to include working examples.

Time trace acquisition - readout pulse#

Description#

In this experiment, a square readout pulse is applied. This pulse should be visible in the acquisition window and can be used to calibrate the timing delay of the integration window.

This experiment can be used to verify the time-trace acquisition functionality of the readout module (e.g., Qblox QRM or ZI UHFQA) is working.

Expected outcome#

A square pulse with some modulation is visible in the integration window.

trace_schedule()

Time trace acquisition - two pulses#

Description#

In this experiment, a square pulse is applied to the microwave drive line. This pulse should be visible in the acquisition window and can be used to calibrate the timing delay between the readout and control pulses.

This experiment can be used to verify the time-trace acquisition functionality of the readout module (e.g., Qblox QRM or ZI UHFQA) is working in combination with the synchronization between the readout module (e.g., Qblox QRM or ZI UHFQA) and the pulse generating module (e.g., Qblox QCM or ZI HDAWG).

Expected outcome#

A square pulse with some modulation is visible on top of a second pulse with a different modulation frequency in the integration window.

two_tone_trace_schedule()

Weighted integration and averaging - Heterodyne spectroscopy#

Description#

Expected outcome#

heterodyne_spec_sched()

Binning and averaging - acquisition staircase#

Description#

Expected outcome#

One would expect to see a monotonic increase in the measured amplitude. The actual amplitudes would probably not match the input amplitudes 1-to-1 because there is likely some loss on the signal path from the up- and down-conversion. Additionally, depending on the overlap between the pulse and the integration window, the average measured voltage will be slightly lower, and the phase can be slightly different resulting in not all signals being in the I-quadrature.

acquisition_staircase_sched()

from quantify_scheduler.schedules.verification import acquisition_staircase_sched

acq_channel = 0
schedule = acquisition_staircase_sched(
    readout_pulse_amps=np.linspace(0, 1, 4),
    readout_pulse_duration=1e-6,
    readout_frequency=6e9,
    acquisition_delay=100e-9,
    integration_time=2e-6,
    port="q0:res",
    clock="q0.ro",
    repetitions=1024,
    acq_channel=acq_channel,
)


comp_sched = compiler.compile(
    schedule=schedule, config=quantum_device.generate_compilation_config()
)

comp_sched.hardware_timing_table

  waveform_op_id port clock abs_time duration is_acquisition operation wf_idx operation_hash hardware_channel clock_cycle_start sample_start waveform_id
0 IdlePulse(duration=1e-06)_acq_0 None cl0.baseband 6.7 ns 1,000.0 ns False IdlePulse(duration=1e-06) 0 -6176082662317231880 None nan nan IdlePulse(duration=1e-06)_acq_0_sample:nan_phase:0.0
1 SquarePulse(amp=0.0,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0 q0:res q0.ro 1,006.7 ns 1,000.0 ns False SquarePulse(amp=0.0,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0) 0 778701891666318335 ic_uhfqa0.awg0 226.0 4.0 SquarePulse(amp=0.0,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0_sample:4.0_phase:0.0
2 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=0,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 1,106.7 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=0,bin_mode='average',phase=0,t0=0) 0 -1414757231151268374 ic_uhfqa0.awg0 249.0 0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0
3 IdlePulse(duration=1e-06)_acq_0 None cl0.baseband 3,113.3 ns 1,000.0 ns False IdlePulse(duration=1e-06) 0 -6176082662317231880 None nan nan IdlePulse(duration=1e-06)_acq_0_sample:nan_phase:0.0
4 SquarePulse(amp=0.3333333333333333,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0 q0:res q0.ro 4,113.3 ns 1,000.0 ns False SquarePulse(amp=0.3333333333333333,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0) 0 1284654502485347327 ic_uhfqa0.awg0 925.0 4.0 SquarePulse(amp=0.3333333333333333,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0_sample:4.0_phase:0.0
5 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=1,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 4,213.3 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=1,bin_mode='average',phase=0,t0=0) 0 -7457024832271362313 ic_uhfqa0.awg0 948.0 -0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0
6 IdlePulse(duration=1e-06)_acq_0 None cl0.baseband 6,220.0 ns 1,000.0 ns False IdlePulse(duration=1e-06) 0 -6176082662317231880 None nan nan IdlePulse(duration=1e-06)_acq_0_sample:nan_phase:0.0
7 SquarePulse(amp=0.6666666666666666,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0 q0:res q0.ro 7,220.0 ns 1,000.0 ns False SquarePulse(amp=0.6666666666666666,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0) 0 5252790970762316826 ic_uhfqa0.awg0 1,624.0 4.0 SquarePulse(amp=0.6666666666666666,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0_sample:4.0_phase:0.0
8 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=2,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 7,320.0 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=2,bin_mode='average',phase=0,t0=0) 0 4084677390208054071 ic_uhfqa0.awg0 1,647.0 -0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0
9 IdlePulse(duration=1e-06)_acq_0 None cl0.baseband 9,326.7 ns 1,000.0 ns False IdlePulse(duration=1e-06) 0 -6176082662317231880 None nan nan IdlePulse(duration=1e-06)_acq_0_sample:nan_phase:0.0
10 SquarePulse(amp=1.0,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0 q0:res q0.ro 10,326.7 ns 1,000.0 ns False SquarePulse(amp=1.0,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0) 0 3556183005496160402 ic_uhfqa0.awg0 2,323.0 4.0 SquarePulse(amp=1.0,duration=1e-06,port='q0:res',clock='q0.ro',reference_magnitude=None,t0=0)_acq_0_sample:4.0_phase:0.0
11 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=3,bin_mode='average',phase=0,t0=0)_acq_0 q0:res q0.ro 10,426.7 ns 2,000.0 ns True SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=3,bin_mode='average',phase=0,t0=0) 0 1269350449748138047 ic_uhfqa0.awg0 2,346.0 0.0 SSBIntegrationComplex(port='q0:res',clock='q0.ro',duration=2e-06,acq_channel=0,acq_index=*,_acq_0_sample:0.0_phase:0.0